Micrel
MICRF405
April 2006
32
M9999-041906
(408) 955-1690
Lock Detect
Adr
Data
A6..A0
D7
D6
D5
D4
D3
D2
D1
D0
0001100 LowBatt_level=0
LDO_by=0
LDO_en1=1
LDO_en0=1 MOD_LDc_en=0 PA_FEc_en=0 PA_LDc_en=0
LD_en=1
0001111 VCO_Fr_Chk=0 VCO_Fr_Auto=0
FSKn2=1
FSKn1=0
FSKn0=0
Mod_F2=1
Mod_F1=0
Mod_F0=0
The lock detector can be enabled by setting
LD_en=1. When pin LD is high, it indicates that the
PLL is in lock. Care must be taken when monitoring
the LD during data transmission using the closed
loop modulation. Due to the fact that the PLL tries to
cancel the modulation signal, there will be some PLL
activity during the transmission time, especially
when the PLL BW is too high relative to the bitrate.
The LD may therefore, show that the PLL is not in
lock.
When starting a transmit session, the LD signal is
helpful in deciding when to turn on the PA. When
going from power down or stand by mode to TX
mode, or after a frequency change, the PLL needs
some time to lock on to the frequency. During this
time it is necessary to keep the PA off. This is done
by setting PA[2:0]=0 and PA_LDc_en=0. When the
LD signal goes high, it is safe to turn on the PA, by
setting the PA[2:0] to the desired output level.
Depending on the output power, and the loop filter,
the LD signal might drop during start up of the PA
due to VCO pulling. When LD is high again it is time
to start the modulation.
The lock detect signal is used internally in several
functions; the VCO_Fr_Chk/Auto, the MOD_LDc and
the PA_LDc. The VCO_Fr_Chk/Auto are described
in detail under the VCO chapter.
PA_LDc (PA Lock Detect Control) is used to
automatically turn on the PA the moment the PLL
has locked on to the frequency. This function is
enabled when the PA_LDc_en bit is set. From power
down or stand by, simply program the MICRF405 to
TX with the wanted PA output setting. The
MICRF405 will then automatically turn on the PA
once the PLL has locked. The PA will remain on until
PA[2:0]=PA_LDc_en=0 or the transmitter leaves
transmit mode (Mode[1:0]<>3). However, the PA is
temporary turned off for every internal load pulse or
if the DATAIN pin is tri-stated in open loop
modulation (Modulation[1:0]=2). This means that if
you want to change frequency, the PA will shut off
during the settling of the new frequency, and then it
is turned on once the PLL has locked on to the new
frequency. It is necessary that LD_en is set for the
PA_LDc function to work.
The correct time to start modulation will be internally
decided when the MOD_LDc (Modulation Lock
Detect control) bit is set. This function is only
working when data is transferred through the SPI
(Bit_IO_en=0). The phase detector frequency (Fphd)
has to be < 200kHz when MOD_LDc is enabled.
Program the MICRF405 in transmit at the proper
output frequency and power strength. Then, write
the frame length of the packet into the data buffer.
The MICRF405 will now delay the modulation until
the PLL has locked with PA turned on. For this
function to work, both LD_en and PA_LDc_en must
be set. This function is especially useful when
transmitting several packets without leaving the TX
mode and the PA_FEc_en bit is set. After a packet
is finished transmitted, the PA_FEc function will turn
the PA off until a new packet is to be sent. If the
MOD_LDc function is not enabled, the modulation
and turning on the PA will then start simultaneously,
there by creating distorted start of packet and
interfering with the settling of the PLL due to PA turn
on. With MOD_LDc enabled the modulation will be
delay until the PLL has locked with PA on.
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